Why Dual-Orin XPengs Can't Run Full VLA 2.0: The Bandwidth Wall

A Zhihu thread that has become the reference reading for XPeng's angriest owners makes a technical argument worth taking seriously — and it is not the argument most people expect.

The question, posted after XPeng's VLA 2.0 launch, is blunt: after VLA 2.0 shipped, why are dual-Orin-X owners getting angrier and angrier?

The top answers are pure grievance. One owner of a 2025 G9 that cost him ¥300,000 on the road in May 2025 notes that six months later the 2026 facelift arrived — and then the new driving model, he was told, had nothing to do with him. Another reply argues that if anyone deserves to be furious it is the old P7 owners still waiting on L3 hardware and the P5 LiDAR buyers. A third tells owners their anger is just selfishness.

The answer summarised here — from Zhihu user 走马观花, third by votes with 43 — starts from the opposite position, then spends several thousand words explaining why the angry owners have a point anyway.

"First ask whether it's true, then ask why. Why be angry? I'm looking forward to the distilled version! Why be unhappy that there's a newer version you can use?"

By the end he has concluded that XPeng could not have done otherwise on the hardware — and could have done considerably better on the communication.

Read this with the right caveat

走马观花 is explicit that his numbers did not come from a lab bench. He says he spent "more than twenty rounds" in deep conversation with DeepSeek, then ran a debate between Gemini, DeepSeek and Claude across several rounds, and he states plainly:

"Many of the details of the Gemini, Claude and DeepSeek debate exceed my knowledge, or I have no way to verify them by engineering. I cannot fully judge."

XPENGTech has verified the chip specifications below against primary sources where they exist — those are marked. The derived figures — effective bandwidth after interconnect loss, sustained inference rates, and the conversions from latency to braking distance — are the thread's own reasoning. Treat them as a community model, not a measurement: directionally useful, numerically soft.

The argument: this is a bandwidth problem, not a TOPS problem

The core claim is that large-model inference is memory-bound, not compute-bound. Every token generated requires reading the model weights once, so what matters is how fast you can move bytes, not how many MACs you can issue.

The thread's arithmetic runs like this. A 30B-parameter model at 4-bit quantisation is roughly 15 GB. To sustain 20 inferences per second — 20 Hz, which the thread treats as XPeng's fluency target — you need:

15 GB × 20 Hz = 300 GB/s

That figure is the whole argument. Compute is not the constraint; moving 15 GB twenty times a second is.

Why dual Orin X cannot get there

The thread concedes the obvious counter-argument and then dismantles it. Two Orin X chips each have their own memory, so naively you have 2 × 205 GB/s ≈ 410 GB/s — comfortably above 300.

The problem is the interconnect. The two chips talk over PCIe Gen4 x16. When the model is split across them in model-parallel mode, intermediate activations and KV-cache have to cross that link constantly. PCIe latency is measured in microseconds; on-die memory in nanoseconds. The thread's analogy is a narrow alley between two warehouses: the warehouses are full, but the alley is the bottleneck.

Its estimate is that 20–30 GB/s of the nominal bandwidth is consumed by chip-to-chip traffic, leaving 150–170 GB/s of net bandwidth for the model — against a 300 GB/s requirement. The verdict: dual Orin X can run the full 30B model only at about 10 Hz, half the target.

The alternative — a 15B intermediate model at ~7.5 GB needing ~150 GB/s — fits on paper but fails on thermal grounds in the thread's analysis. Long runs near the bandwidth ceiling push the chips into thermal throttling, PCIe latency fluctuates, and the perception/planning/control stacks are competing for the same bandwidth anyway. Its summary is that 15B on dual Orin X is "fast sometimes, slow sometimes" — not shippable.

A 4–7B distilled model needs only 40–70 GB/s, leaving 100 GB/s of headroom. No throttling, no dropped frames, consistent behaviour. Hence distillation is not a punishment but the optimal engineering answer for that platform.

Why Turing can

The XPeng Turing chip is rated at 273 GB/s, and the thread makes a second point that matters more than the raw number: in a three-Turing vehicle, the two chips assigned to driving are joined by a dedicated ring interconnect rather than PCIe. That traffic does not consume DRAM bandwidth, so nearly all 273 GB/s is available to the model.

Even so, 273 GB/s sits below the 300 GB/s the thread says a 30B model wants at 20 Hz. Its answer is model-side optimisation — tighter quantisation, operator fusion — to close roughly a 30 GB/s gap and land at 7–10 Hz with 100–150 ms latency.

The specs, with what is actually verified

Chip	AI compute	Memory bandwidth	Status
NVIDIA Drive AGX Orin	254 INT8 TOPS (verified)	205 GB/s LPDDR5 (verified)	In production
NVIDIA Drive AGX Thor	1,000 INT8 TFLOPS (verified)	273 GB/s LPDDR5X (verified)	Current generation
XPeng Turing (single)	750 TOPS effective (verified)	273 GB/s (reported)	In production
NIO Shenji NX9031	~1,000 TOPS (vendor)	546 GB/s (vendor)	In production
Tesla HW4	Not disclosed	~448 GB/s (teardown)	In production
Huawei MDC 610	200+ TOPS INT8 (vendor)	308 GB/s (unverified)	In production

Verification notes: Orin's 254 TOPS and 205 GB/s, and Thor's 273 GB/s, come from NVIDIA's own developer documentation. XPeng's 750 TOPS, 40-core, 30B-parameter-capable Turing specs come from XPeng. NIO's 546 GB/s over a 512-bit LPDDR5X interface at 8533 Mbps comes from NIO. Tesla's ~448 GB/s comes from teardown reporting of eight GDDR6 modules. The 308 GB/s figure for Huawei's MDC 610 could not be confirmed in any primary or teardown source we found — Huawei documents the chip at 200+ TOPS but does not publish a bandwidth figure. Treat that row as unverified.

The uncomfortable finding buried in the table

The thread draws a conclusion that cuts against the car it is defending. If these figures hold, Turing's 273 GB/s is not class-leading: it sits below Tesla HW4 (~448 GB/s) and well below NIO's Shenji (546 GB/s), and — on the thread's unverified number — below Huawei's MDC 610.

It is also, precisely, the same bandwidth as NVIDIA's Thor (273 GB/s LPDDR5X). Whether that is convergence on the same LPDDR5X memory class or something else, it means XPeng's in-house silicon is compute-rich and bandwidth-modest relative to the field. The thread's own framing is that XPeng "compromised on bandwidth" as a cost-and-power decision, making Turing's bandwidth "just barely enough" rather than "comfortably surplus."

The safety framing

The most emotionally loaded part of the argument is the conversion from hertz to metres. At 108 km/h — 30 m/s — a 20 Hz decision loop updates every 1.5 m, while 10 Hz updates every 3 m. The thread describes that 1.5 m difference as potentially "the line between an accident and safety" in complex conditions.

Stated that way it is rhetorically strong and technically loose. A 1.5 m difference in update interval is not a 1.5 m difference in stopping distance, because braking, steering and the perception stack run on their own loops and the vehicle does not act only at model-update boundaries. The underlying point — that halving inference rate degrades reaction margins at speed — is sound. The specific metrage should not be quoted as a braking-distance delta.

The commercial ladder, and what rivals tell buyers

The thread reads XPeng's own price list as the honest version of the argument. From the G6 launch information it cites:

Configuration	Turing chips	Price
Max	1	from ¥186,800
Ultra SE	2	+¥12,000
Ultra	3	+¥20,000

Its gloss: "want better hardware, pay more" — and by implication, a car bought at the Max price point bought a bandwidth budget, not just a chip count.

It then contrasts how other brands manage the same expectation:

• NIO ET9 (¥818,000): Shenji at 546 GB/s, and NIO is willing to say it "supports ten years of evolution."
• NIO ET5T (¥165,000, clearance): buyers are told to wait for the NT3.0 platform; no forward commitments.
• Huawei Aito M9 (¥469,800): four LiDARs plus MDC810, with L3 "expected to unlock within 2026."
• Huawei Shangjie H5 SE (¥159,800): pure vision, and stated as permanently unable to upgrade to L3/L4.

The thread's conclusion is that Huawei is the most honest communicator in the market: the price you pay determines how far you can be OTA'd, said out loud, even when it stings.

The timeline — and how it actually went

The answer's most checkable section is its roadmap, drawn from He Xiaopeng's 16 March livestream:

When	What ships	Which cars
From 19 March 2026	First full VLA 2.0 wave	P7 Ultra, G7 Ultra, X9 Ultra and Ultra SE
April 2026	Second full VLA 2.0 wave	2026 P7+, G9, G6 Ultra and Ultra SE
H2 2026	Distilled VLA	Single-Turing Max first, then dual-Orin X Max

He Xiaopeng's accompanying positioning, per the thread: Max is aimed at being excellent at L2; Ultra is aimed at L4. Read uncharitably, that is a statement that Max buyers should not expect the frontier. Read charitably, it is the clearest sentence anyone at XPeng has said about hardware tiers.

That projection has largely held. Reporting in late August 2026 put the distilled VLA 2.0 Lite on a September rollout with the G9L Max as the launch model — the single-Turing step first, exactly as described. (We drove the distilled dual-Orin build in a MONA M03 here.)

What is actually worth taking from this

1. The framing is right even if the numbers are soft. "Why can't my car run it" is a memory-bandwidth question before it is a compute question, and almost no marketing material in this industry frames it that way.
2. The communication critique is the strongest part. The thread's own conclusion is that XPeng's hardware decision was defensible, and its messaging was not: owners were told "a distilled version is coming in the second half of the year" without capability boundaries, a schedule, or a technical reason. That is a fixable problem.
3. Compute figures are the wrong scoreboard. 750 versus 1,000 TOPS tells you far less about what a car can run than the bandwidth number, which is soldered down and cannot be improved by software.
4. The anger is about depreciation, not physics. The technical explanation may be entirely correct and still not address why someone who paid ¥300,000 fifteen months ago now watches a cheaper car get a better model. Those are separate arguments, and only one of them is about PCIe.

Caveats, stated plainly

This article summarises and translates a community analysis published on Zhihu on 16–17 March 2026 by user 走马观花. It is not official XPeng information, and the author says himself that most of the analysis was produced with AI assistance and that he cannot verify it.

The verified items are the vendor and teardown specifications quoted in the table and its notes. Everything else — effective bandwidth after interconnect loss, the 20 Hz fluency target, sustained inference rates, the 100–150 ms latencies, the thermal-throttling behaviour, the 15B intermediate model, the price ladder, and all conversions from hertz to metres — is the thread's reasoning and has not been independently confirmed.

The Huawei MDC 610 bandwidth figure could not be sourced and should not be repeated as fact. The hertz-to-metres conversions simplify a real control system into a single update interval and should not be read as stopping-distance differences.

XPeng's own claims about Turing's capability are XPeng's claims. VLA 2.0 performance in a customer car depends on the shipped build, the road, and the weather.

Source: 走马观花, Zhihu — translated & adapted for XPENGTech. Read the original answer.