Inside XPENG's Paris 'Revenge': Cloud, Edge and the Australian Deployment

The Weibo essay that calls the Paris Motor Show XPENG's "revenge" is not really about the show. Strip out the scorekeeping and it is an argument about compute: a 72-billion-parameter teacher in the cloud, a car-sized student on the road, and a European adaptation recipe measured in weeks rather than years. That is the part worth reading closely — and it is also the part that decides when any of this reaches Australia.

Parts two and three of the series, published on 30 and 31 October, turn to XPeng's rivals' infrastructure problem and to the 2027–28 endgame; they are covered in new sections below.

The event first, briefly. The 2026 Paris Motor Show added an official public autonomous-driving lab, and only two manufacturers accepted: Tesla, with Model 3s running FSD Supervised, and XPENG, with MONA L03s running the second-generation VLA. No European manufacturer took part. He Xiaopeng flew in to test NGP himself and asked for France's worst routes. Before Paris, Xinhua ran a same-route comparison in Amsterdam and called the two systems "hard to separate" — the one difference it singled out was a construction zone where Tesla reversed to adjust and XPENG judged the gap and went. That is the scoreline: two systems that both worked, with different margins. The technology underneath is more interesting.

A cloud teacher, a car-sized student

The essay's central claim is architectural. Most Chinese driver-assistance systems that went the large-model route use a two-stage design: cameras capture the scene, a vision-language model converts what it sees into text-like tokens, and a planner reasons over those tokens before issuing a driving action. That intermediate language layer is convenient for humans to inspect and expensive for a car: it adds latency between seeing and acting, and it ties the system to the road signs and traffic language of the country it was trained in.

XPENG's second-generation VLA, according to its launch material and to Liu Xianming, who runs the company's General Intelligence Center, removes that layer. The chain becomes visual input → physical geometry and motion understanding → driving action, with the claim that end-to-end decision latency falls from roughly 200 ms to under 80 ms and inference efficiency improves 12-fold. Whether those exact numbers survive independent measurement is open; the design choice is what matters, because the physics of a pedestrian stepping out or a truck braking does not change between countries, while the text on a sign does.

Then there is time. The August 2026 upgrade added what XPENG calls Infini-VLA, which keeps about 30 seconds of road context in the model, and X-Foresight, a world model that predicts about six seconds ahead. Both run on the car, in a streaming, autoregressive way: the car is not waiting for a cloud round-trip to decide. That is the edge half of the architecture, and it is the half a driver actually feels.

The compute asymmetry

The essay's numbers on the cloud side are the loudest, and the least checkable. XPENG has publicly described a 72B cloud foundation model — a scale that is unusual for driver assistance and one the company has talked about since 2025 — and the essay adds claims that XPENG keeps its training clusters at 90% utilisation, runs a full retraining cycle about every five days, and operates roughly 10 EFLOPS against Tesla's 100-plus.

The last three are the essay's arithmetic, not published figures, and should be read as such. But the asymmetry it describes is real in direction: Tesla's Cortex cluster is a very large, US-based training asset, and export controls make it hard for a Chinese manufacturer to buy the same class of Nvidia compute at the same scale. XPENG's answer is to spend less on cloud and more on the car: train the big model in China, distill what it has learned into a model small enough to run on the vehicle, and add on-car compute.

That is what the Turing chip is for. New global models get three of them, 2,250 TOPS combined, with the L03 onwards as the reference. The essay claims 216 GB of shared memory and a 30B-parameter local model; XPENG's public material says the chip can run models up to 30B, and the G9L launch described a 3.5× increase in on-car model parameters without giving a parameter count. The confirmed hardware number is 2,250 TOPS. The distillation pipeline is the bridge between the cloud model and that hardware, and it is also why the trim levels differ: on the L03, the Max variants get one Turing chip with 750 TOPS and a VLA Lite model, while the Ultra variants get two chips, 1,500 TOPS and the full VLA. Below the three-chip cars there is a real ceiling, and the trim you buy determines which one you get.

The last piece is the compiler. XPENG says its Turing chip is a domain-specific architecture that went into mass production in 2025 — the essay dates the first Turing DSA to 2025 — and that hardening model operators into silicon, and keeping the compiler from falling back to slower generic paths, is a year-long engineering grind that money alone does not shorten. That claim is hard to verify from outside, but it explains why the company frames its lead as engineering time rather than a single benchmark. It is also the part of the story with a commercial footprint: Volkswagen is reported as the first external customer for the second-generation VLA, a software relationship rather than a wholesale switch of VW's compute hardware.

What that means on Australian roads

Australia is one of the markets XPENG says it designed the L03 for, not one it adapted afterwards. The car launched here and in New Zealand on 12 October from A$41,900, with the extended-range version alongside the battery-electric one: a 37.2 kWh pack and a 1.5-litre engine, 215 km of WLTP electric range and 1,017 km combined, 178 kW and 0–100 km/h in 6.8 seconds, and 123 kW DC charging. It is the first XPENG sold here with the company's in-house AI stack under the skin, and the first from China and the APAC region to integrate Google Maps Auto SDK.

The hardware distinction matters more than the price. XPENG's Australian material says the L03's Ultra variants run two Turing chips with up to 1,500 TOPS, and that the second-generation VLA is planned to arrive overseas by over-the-air update from 2027. Australian reporting puts a finer point on it: only the L03 Performance Ultra carries the NGP-ready Turing hardware, while the rest of the range runs XPilot — adaptive cruise, lane centring, lane-change assistance, traffic-sign recognition and parking assistance. If you buy a lower L03, you are not buying a car that will later receive the full VLA system; the hardware for it is not in the car.

The Australian rollout is not waiting on an approval. Cars with adaptive cruise, lane centring and lane-change assistance are already sold here, and a supervised system of this kind is not the point at which Australia's vehicle rules need to clear it; the automated-vehicle safety reforms being developed by the National Transport Commission are aimed at higher levels of automation, where the car rather than the driver is responsible. XPENG's NGP with VLA 2.0 is a supervised L2++ system: the driver remains responsible. What is missing in Australia is the software release — XPENG's global VLA 2.0 rollout, planned by over-the-air update from 2027 — and the hardware, the Performance Ultra's dual Turing chips. Those are product and supply decisions, and they explain the 2027 date better than any regulatory queue.

The other side of deploying here is calibration, and XPENG has been doing it. It says it has been testing and calibrating XPilot on Australian and New Zealand roads since early 2026, with three named priorities: avoiding vulnerable road users, understanding local road signs, and understanding what its local team calls implicit traffic rules — the things Australian drivers do that are not written in a rulebook. Parking is being adapted to shopping-centre carparks, tight kerbside spaces and home garages. The company's wider local programme covers vehicle dynamics, software, data, mapping and navigation, and it continues after launch. The L03 was engineered to meet five-star safety standards in China, Europe and Australia simultaneously, which for a family SUV here matters at least as much as the compute headline.

Data is the quieter deployment question. XPENG's European approach, as the essay describes it and as Liu Xianming has discussed publicly, is to train the 72B base model in China and then adapt it per country using a very small local dataset — about 1/10,000 of the foundation-model data, with roughly two weeks of work per new European country, according to Liu's Bloomberg interview. For Australia the same architecture applies, but the compliance frame is different: Australia has no general data-localisation mandate, while the Privacy Act's Australian Privacy Principles require transparency about cross-border disclosure and reasonable steps before personal information goes overseas. Running the local adaptation on Australian cloud capacity — AWS has a Sydney region, as do Alibaba Cloud and Azure — is technically straightforward; whether XPENG does it locally or in China is a policy choice, not a physics constraint. The company has not said which it will do here.

What does the edge-versus-cloud split mean for an Australian owner in practice? It means the car's driving decisions do not need mobile coverage, which matters on the Hume between towns and on regional roads where signal drops. It means map and voice features still depend on connectivity, which is why XPENG's executives have talked about offline voice support in markets where data is expensive and carriers bill slowly. And it means the quality of the local adaptation — the two-week, small-dataset recipe — is the thing that determines how the car behaves on a country road with no lane markings, or in a car park in Penrith, rather than the number of TOPS on the brochure.

What to watch

• The 2027 L03 Performance Ultra deliveries. Whether the VLA 2.0 over-the-air update arrives on the timetable XPENG has given, and whether every Performance Ultra sold here has the hardware it needs.
• What happens to the rest of the range. Max trims and older Orin-based G6 and G9 cars in Australia have no committed path to the full model; the distilled Orin version XPENG has discussed is a China rollout.
• Where the data is processed. A local-region training/adaptation announcement would tell Australian buyers more about the long-term commitment than any statement about the car's compute.
• The higher-automation tail. The NTC's automated-vehicle reforms and the UN ADS GTR matter for L3 and beyond; they are not what stands between an Australian buyer and supervised VLA 2.0.

Part two: the infrastructure exam

Part one argued that XPeng's Paris demo showed a full-stack physical-AI loop running a year early. The middle part of the series — published on 30 October as 【中篇·阵痛】, "middle volume: the growing pains" — asks the inverse question. If that loop is now the standard, what are Li Auto, DeepRoute, Momenta, Horizon and Huawei missing?

The answer, the essay says, is infrastructure (基建): a three-part bundle of AI-native talent, "dedicated silicon sovereignty" (its own chip), and a deep compiler toolchain. It is the compiler, not the chip, that the essay treats as the real moat — because a compiler is what turns a model's operators into silicon and keeps them from falling back to slower generic paths. The essay sets its own limit: it calls itself a technical-trend推演, an exercise in inference, and says it does not dispute anyone's current delivery or local commercial standing.

A 40B model with nowhere to run

The first case is DeepRoute.ai (元戎启行), a leading third-party city-NOA supplier by the essay's account. It quotes CEO Zhou Guang from an October conversation: the shift to large models is not a matter of changing chips but of "changing people", because a small model is a dead end. Fix it and you get a seesaw — repair city A and city B breaks — with takeover distance stuck around the 100-kilometre level. He credits XPeng's move to the large-model paradigm with a 13-fold improvement in takeover mileage, and says the old method could never have got there.

DeepRoute's response, per the essay, was structural: it hired Ruan Chong, a former DeepSeek researcher, as chief scientist, and is building a 40B-parameter base model that folds driving, scene commentary and coach-style correction into one system, aimed at 1,000 km between interventions (MPCI).

Then the constraint. The essay argues that Nvidia's Thor may not beat the older Orin in practice — not because the silicon is weak, but because a small model cannot absorb the compute, and because equal TOPS does not come with matching software. A 40B model cannot run directly on a general-purpose automotive chip whose instruction set and compiler must serve every customer; it has to be distilled down to fit, and once it is distilled, Thor's extra headroom buys little. The essay's image is a large apartment whose load-bearing walls do not match your equipment.

Checkable: DeepRoute did appoint Ruan Chong as chief scientist and has publicly committed to the large-model route (证券时报, April 2026). The 40B figure, the 13× claim and the Thor-versus-Orin comparison are the essay's and its interview's, not independent measurements.

Li Auto: the silicon is ahead of the compiler

The second case is Li Auto, which has done the hardware work. Its Mach M100 is a 5-nanometre automotive chip with 1,280 TOPS per die and 2,560 TOPS across a dual-chip package, built on a dataflow architecture with no cache and a claimed 82% utilisation. In July 2026 Li Auto became the first Chinese automaker to present a paper at ISCA; the chip is already shipping in the new L9 and L8, and the 2026 i6 launched on 28 October with one M100 as standard and a dual-chip option.

The essay's argument is that the hard part starts after the silicon. M100's utilisation depends on the compiler scheduling data flow statically; when the model adds new VLA operators, a compiler that cannot keep up triggers operator fallback, and utilisation can collapse from about 80% to 30%. That is a claim about a specific toolchain, not something visible from a spec sheet. The essay also points to people: Li Auto's base-model head, Chen Wei, was reported to be leaving, with Zhan Kun taking over, and the software R&D head of the chip division, Jin Yihua, has left — both reported by Chinese tech media this year. The essay estimates 12 to 18 months, into late 2027, before the dual-M100 stack is fully tamed. XPeng, it notes, went through the same operator-hardening and compiler grind with its first-generation Turing chip in 2025 — which is why it frames its lead as engineering time rather than a benchmark number.

Checkable: the M100 specifications, the ISCA paper and the two departures are reported. The 273 GB/s bandwidth figure, the 80%-to-30% fall and the 12–18 month estimate are the essay's analysis.

Huawei: winning the market, carrying the legacy

The third case is the one the essay treats most carefully, because it is the incumbent. It credits Huawei's ADS with engineering execution, brand power and a mature stack — high-definition or light maps, rule-based fallbacks, lidar redundancy — and then argues that the same assets become constraints in the next paradigm:

• Hardware redundancy versus an end-to-end stack. Lidar and a heavy rule layer cost BOM and engineering attention; moving to a vision-native VLA means either carrying that legacy or rebuilding the stack while keeping a million-car fleet stable.
• "Everywhere in China" does not travel. The domestic experience comes partly from local engineering teams and regional tuning of long-tail bugs — a real moat inside China, and a diminishing one when the task is zero-shot adaptation to another country's roads.
• The overseas bind. Europe and the Middle East lack China's mapped road base and bring GDPR-style limits on vehicle data, so a stack that depends on local mapping and heavy local engineering moves slowly abroad. The essay's answer is a native architecture: a cloud base model distilled at home, an on-car VLM doing local semantic adaptation, and lightweight overseas cloud fine-tuning.

Checkable: this is the essay's argument, not a Huawei claim, and the essay does not name a Huawei product that lacks these pieces. Huawei's own overseas plans and any VLA work are not addressed.

The exam question

The essay concludes that domestic commercial scale can be defended with engineering execution and hardware stacking, but the ticket to the 2027–28 global L4 table belongs to whoever closes the full infrastructure loop: AI-native talent, a 72B-class cloud base model, self-developed DSA silicon and a deep compiler. It promises a third part on the endgame — the physical limits of three and four Turing chips, Tesla's AI5 chip and FSD V15, and XPeng's next-generation Turing.

For the Australian question in part one, the implication is narrow but real. If the bottleneck is the compiler and the toolchain rather than the TOPS figure on the brochure, then the pace of over-the-air updates and per-market adaptation is the thing to watch — which is consistent with the two-week, small-dataset adaptation recipe part one described for new European markets.

The essay is explicitly a推演 and says so. Its case studies are unevenly checkable: the chips, the departures and DeepRoute's pivot are reported; the utilisation collapses, the 40B model and the 2027–28 dates are forecasts. We have kept its attributions and marked the line.

Part three: the endgame, and the chip count

The final part (【下篇｜终局对决】, 31 October) opens by clearing the table: the second tier of the industry — the companies buying general-purpose chips and patching behaviour with rules — is either leaving the mainstream game or sprinting to rebuild around large-model infrastructure. What remains, the essay argues, is a 2027–28 fight between Tesla and XPeng, and the prize is not better L2 assistance but regulatory-grade L4 and the private car as a revenue machine.

Three chips or four

It starts from two things XPeng has just done. The first is unlocking a third Turing chip on its production flagships (G9L and GX Ultra) with XOS 6.3.0, which the essay says lifts the on-car VLA's parameter count 3.5-fold — 15 times a mainstream on-device small model — and folds the driving VLA and the cabin's Omni-VLM into one "Master Agent". The second is the four-chip (3,000 TOPS) Yoyo Robotaxi and its city-wide L4 demonstration licence in Guangzhou, which the essay frames as the second company after Tesla to put a vision-only, production L4 car on the road.

Then the question its readers ask: if three chips (2,250 TOPS, 216 GB, up to a 30B local model) share the same brain as four, why is three "quasi-L4" and four a driverless Robotaxi? The essay's answer is a physical boundary, and the boundary is redundancy. Three chips are fully allocated: two run the 4D vision stack, one runs the driving-and-cabin fusion. In a private car, a chip failure can hand control back to the human. In a driverless car at 120 km/h, it cannot: the essay raises a single-event upset — a cosmic-ray bit flip — and says the Robotaxi therefore carries a fourth, independently powered Turing chip (750 TOPS) as a shadow backup that takes over the chassis within 10 milliseconds. Without that chip, three Turing is "the peak of supervised quasi-L4"; with it, four crosses the regulatory line for unmanned commercial operation.

The second boundary is memory. Both three- and four-chip cars use the first-generation Turing, with 273 GB/s per die, and the essay argues that re-reading the KV cache every millisecond caps practical continuity at roughly 30 seconds of history plus 6 seconds of prediction. For a ground-level city Robotaxi with 5G and cloud road-network help, 30 seconds covers almost all of the cut-in game. For "all-space-time L4" in 2028 it does not, and the essay lists four places where a 30-second memory develops amnesia: a GPS-denied three-level underground car park, a 200-metre dead-end alley that has to be reversed out of, a construction closure that produces a loop, and a 2 km contraflow around roadworks where the "contraflow permitted" sign has been forgotten. These are the argument for the next silicon, not the current one.

Tesla's cards

The essay then lays out what it expects from Tesla in 2027: AI5, on TSMC 3 nm or Samsung 2 nm, about 2,500 TOPS per die with twelve HBM stacks and 1.5–2 TB/s of bandwidth, a single large die to remove the cost of stitching several together; and FSD V15, which it says grows parameters tenfold, cuts reaction time to 0.13 s, intervenes from up to 300 m ahead, abandons third-party maps for a fleet-built "AI-native crowd memory map", and, in Q2 2027, lets ordinary Model Y owners opt their cars into the Robotaxi network. These are forecasts and leaks, not published specifications — the essay presents them as Tesla's direction of travel, and the reader should treat them that way.

XPeng's counter, as the essay predicts it

The final section is explicitly labelled a 前瞻推演 — a forward deduction from semiconductor physics and model scaling — and it is the most speculative part of the series. Constrained by the domestic foundry ceiling (probably still a 5 nm-class process in 2027) and a cloud budget about a tenth of Tesla's, XPeng cannot win by stacking more first-generation chips, the essay argues. Its predicted three moves:

• Silicon: a chiplet package (two dies joined by nanosecond links) with native FP4 and faster memory, pushing one package to 1,500–2,000 TOPS and about 1 TB/s, plus a hardware KV-cache compression engine inside the NPU to stretch memory from 30 seconds to 10+ minutes. Two of those chips (3,500–4,000 TOPS) would be enough for full L4 hot standby, bringing L4 hardware into 200,000-yuan cars.
• Models: on the car, a 100B+ sparse MoE that activates about 10B parameters per frame — a hospital of specialists rather than one generalist — with latency under 30 ms; in the cloud, a base model beyond 72B plus self-play reinforcement learning inside X-Foresight's simulated arena.
• One architecture for car and robot: a Turing instruction set that unifies the car's chassis control and IRON's joint control by 2028, so the same brain drives the car and the humanoid. The scenario the essay paints: a 200,000-yuan car drops you at work, runs Robotaxi trips, charges itself, washes itself, and is outside the office at six.

What is checkable here

• The third chip and XOS 6.3.0 are real XPeng releases; the 3.5× parameter claim is XPeng's, and the "Master Agent" framing is the company's.
• The Yoyo licence is documented — but it is a demonstration-operation qualification, with invitation codes, not the mass commercial L4 the essay's word "production" implies. Our report on the licence has the detail.
• 273 GB/s and the 30-second memory wall are the essay's inference from first-generation Turing's bandwidth, not published XPeng numbers.
• AI5, V15, the 10-minute KV-cache engine and the 200,000-yuan L4 car are forecasts. The essay says its third section is speculation; we have kept that label.
• The essay is the final part of the series, and it ends without a further trailer.

The endgame in one line

Strip the spec sheets and the argument is about cost and redundancy: the 2027–28 fight belongs to whoever can put a redundant, long-memory, cheap L4 stack into a mass-market car, and only Tesla and XPeng are attempting it with in-house silicon, in-house models and their own fleet data. Whether XPeng's chiplet-and-FP4 path arrives on that schedule — and at that price — is the open question; the essay's value is in naming the boundaries rather than predicting the winner.

The original post

The series is 彦山堂's 全时空自动驾驶路在何方 — "where does all-space-time autonomous driving go?" — on Weibo (uid 5365308769).

Part one, "Paris Revenge" (29 October), reads as three layers: the language-free VLA 2.0 architecture, the cloud-versus-edge compute strategy (a 72B cloud teacher, 2,250 TOPS of Turing silicon on the car, rented overseas cloud for European adaptation under GDPR), and the compiler work that turns operators into silicon.

Part two, 【中篇·阵痛】 (30 October; 2 reposts, 4 comments and 7 likes at 15:50 Beijing on 31 October), is the infrastructure survey: DeepRoute's 40B model with nowhere to run, Li Auto's compiler problem, and Huawei's path dependency.

Part three, 【下篇｜终局对决】 (31 October; 1 comment and 6 likes), is the endgame: the three-versus-four Turing boundary, Tesla's AI5 and FSD V15, and a predicted next-generation XPeng stack. Its first two sections are the author's reading of current hardware; its third is explicitly a推演.

The author's note describes the series as a technical-trend推演 overall: the Paris test, chip specifications and licences are checkable facts, while the 2027–28 timings are not. The series is complete.

Read the originals: part one, part two and part three.